1. Field of the Invention
The present invention relates to a multiplier, and more particularly, to an improved multiplier for multiplying n bits and n/2 bits in accordance with a word control signal.
2. Description of the Background Art
FIG. 1 is a construction view illustrating a conventional multiplier for performing a word multiplication and a byte multiplication, wherein an expansion of two numbers multiplication is implemented using a long-hand form. In order to multiply the two numbers using the long-hand form, a multiplier and a multiplicand are appropriately aligned in number digits. The respective number digits of the multiplier are multiplied by those of the multiplicand and the results are aligned on the basis of the number digits of the multiplier and then the aligned results are appropriately added to obtain the final result.
Using the long-hand form, the product of an 18-bit word A[17:0] and an 18-bit word B[17:0] is obtained as follows:
Here, A[17:9] and B[17:9] represent the upper byte and A[8:0] and B[8:0] represent the lower byte of the words A[17:0] and B[17:0], respectively. The expansion of the above is a well-known process and accordingly its discussion will be omitted.
As shown in FIG. 1, the conventional multiplier includes: an input port 100 receiving an 18-bit word A[17:0]; an input port 104 receiving an 18-bit word B[17:0]; a port 102 dividing the 18-bit word A[17:0] into a 9-bit upper byte A[17:9] and a 9-bit lower byte A[8:0]; a port 106 dividing the 18-bit word B[17:0] into a 9-bit upper byte B[17:9] and a 9-bit lower byte B[8:0]; an input port 108 receiving a select signal DEL; a multiplexer 110 receiving the select signal SEL and the 9-bit upper byte A[17:9] of the 18-bit word A[17:0]; a multiplexer 114 receiving the select signal SEL and the 9-bit lower byte B[8:0] of the 18-bit word B[17:0]; a 9-bit multiplier 112 receiving the 9-bit lower byte B[8:0] and the output signal of the multiplexer 110; a 9-bit multiplier 116 receiving the 9-bit lower bytes A[8:0] and B[8:0]; a 9-bit multiplier 118 receiving the 9-bit upper bytes A[17:9] and B[17:9]; a 9-bit multiplier 122 receiving the 9-bit upper byte B[17:9] and the output signal of the multiplexer 114; a concatenation port 120 connecting the respective output signals of the 9-bit multipliers 116, 120; an adder 124 adding the respective output signals of the 9-bit multipliers 112, 124; a concatenation port 126 generating a 36-bit output signal by inserting a plurality of xe2x80x980xe2x80x99s into the upper 8 bits and lower 9 bits in the output signal of the adder 124; a 36-bit adder 128 adding the respective output signals of the concatenation ports 120, 126; and an output port 130 receiving an output signal of the 36-bit adder 128.
The operation of the thusly constituted conventional multiplier will now be described.
When the 18-bit word A[17:0] is applied to the input port 102 and the 18-bit word B[17:0] is applied to the input port 104, the 18-bit word A[17:0] is divided into the 9-bit upper byte A[17:9] and the 9-bit lower byte A[8:0] in the port 102, and the 18-bit word B[17:0] is divided into the 9-bit upper byte B[17:9] and the 9-bit lower byte B[8:0] in the port 106.
At this time, when the select signal SEL becomes a high level, the multiplexers 110, 114 become activated, whereby the respective 9-bit multipliers 112, 116, 118, 122 are operated to perform a 18-bit multiplication. That is, A[17:9]*B[8:0] is performed in the 9-bit multiplier 112 in the 9-bit multiplier 112, A[8:0]*B[8:0] is performed in the 9-bit multiplier 118, and A[8:0]*B[17:9] is performed in the 9-bit multiplier 122. The 18-bit output signals from the 9-bit multipliers 118, 116 are converted to 36-bit output signals (A[17:9]*B[17:9]+A[8:0]*B[8:0]) in the concatenation port 120.
Also, the 18-bit signals from the 9-bit multipliers 112, 122 are added in the adder 124 which then outputs the 19-bit output signal (A[17:9]*B[8:0]+A[8:0]*B[17:9]). Here, the 19-bit output signal is larger than the 18-bit signal applied to the adder 124 since a carry is included.
In the concatenation port 126, a plurality of xe2x80x980xe2x80x99s are inserted into the upper 8 bits and the lower 9 bits of the 19-bit output signal from the adder 124, whereby the 36-bit output signal is generated.
Also, in the adder 128, the respective 36-bit output signals from the concatenation ports 120, 126 are added (A[17:9]*B[17:9]+(A[17:9]*B[8:0]+A[8:0]*B[17:9])+A[8:0]*B[8:0]) a 36-bit output signal Z[35:0]. Here, for convenience""s sake, 2""s exponents representing number digits are not exposed.
Meanwhile, when the select signal SEL is at a low level, the multiplexers 10 1 10, 114 do not become activated so that the respective 9-bit multipliers 112,122 do not output the output signals, whereas the 9-bit multipliers 118, 116 become activated for thereby outputting the results of A[17:9]*B[17:9] and A[8:0]*B[8:0].
As discussed above, the multiplication results are transmitted in 18-bit output signals to the 36-bit adder 128 through the concatenation port 120.
At this time, the 18-bit upper byte Z[35:18] of the 36-bit output signal from the 33-bit adder 128 is identical to the 18-bit output signal (A[17:9]*B[17:9]) from the 9-bit multiplier 118, and the 18-bit lower byte Z[17:0] is identical to the 18-bit output signal (A[8:0]*B[8:0]) from the 9-bit multiplier 116. Here, for convenience""s sake, 2""s exponents representing number digits are not multiplied to the result of the 18-bit output signal. Therefore, the conventional multiplier performs 9 bits multiplication and 18 bits multiplication.
However, the conventional multiplier performs four 9-bit multipliers and one 18-bit adder and one 36-bit adder for the 9 bits and 18 bits multiplication, thereby incurring a slow operation speed and disadvantageously requiring a large circuit size.
The present invention is directed to overcoming the conventional disadvantages. Therefore, it is an object of the present invention to provide a multiplier, capable of performing fast word and byte multiplications by providing a simplified circuit.
To achieve the above-described object, there is provided a multiplier for multiplying n bits and n/2 bits wherein a word multiplication is implemented by input of two words according to the present invention which includes input ports receiving the two words, a port dividing a word at one of the input ports into an upper byte and a lower byte, a port receiving a word control signal, a first encoder receiving the lower byte and a word control signal and outputting a first encoding signal and a second encoding signal, a second encoder receiving the upper byte and the word control signal and outputting a third encoding signal and a fourth encoding signal, a first gating unit receiving the lower byte and a most significant bit of the word and outputting the bit to a carry input terminal of the second encoder in accordance with the word control signal, a partial product generating unit including submodules receiving the first to fourth encoding signals and the word control signal and generating partial products, an operating unit dividing the partial products into a first sum signal, a second sum signal, a first carry word signal and a second carry word signal, a first adder receiving the first sum signal and the first carry word signal and outputting a first carry and a first output signal, a second adder receiving the second sum signal and the second carry word signal and outputting a second carry and a second output signal, a second gating unit receiving the first carry and transmitting the first carry to the second adder in accordance with the word control signal, and an output port outputting the first output signal and the second output signal.
Further, to achieve the above-described object, there is provided a multiplier for multiplying n bits and n/2 bits wherein a word multiplication is implemented by input of two words according to the present invention which includes input ports receiving the two words, a port dividing a word at one of the input ports into an upper byte and a lower byte, a port receiving a word control signal, a first encoder receiving the lower byte and a word control signal and outputting a first encoding signal and a second encoding signal, a second encoder receiving the upper byte and the word control signal and outputting a third encoding signal and a fourth encoding signal, a partial product generating unit including submodules receiving the first to fourth encoding signals and the word control signal and generating partial products, an operating unit dividing the partial products into a first sum signal, a second sum signal, a first carry word signal and a second carry word signal, a first adder receiving the first sum signal and the first carry word signal and outputting a first carry and a first output signal, a second adder receiving the second sum signal and the second carry word signal and outputting a second carry and a second output signal, and an output port outputting the first output signal and the second output signal.
Still further, to achieve the above-described object, there is provided a method for multiplying n bits and n/2 bits wherein a word multiplication is implemented by input of two words according to the present invention which includes a first step for applying a 16-bit first word and a 16-bit second word to two input ports and dividing the first word among the first and second words into an 8-bit upper byte and an 8-bit lower byte, a second step for receiving the 8-bit lower byte and the 8-bit upper byte, generating a pair of 4-bit first, second and third encoding signals, and a pair of 4-bit first, second and third word encoding signals when the word control signal is at a high level, and generating a pair of 4-bit first, second and third encoding signals when the word control signal is at a low level, a third step for transmitting the most significant bit of the lower byte to the encoder outputting the 4-bit first, second and third encoding and word encoding signals when the word control signal is at a high level, a fourth step for receiving the first to third encoding signals and the first to third word encoding signals and the word control signal, generating a word partial product when the word control signal is at a high level, and generating a byte partial product when the word control signal is at a low level, a fifth step for receiving the partial products and dividing the same into respectively two upper word partial products, the lower word partial products, the upper carry word partial product and the lower carry word partial product, a sixth first step for adding the lower word partial product and the lower carry word partial product, a seventh step for adding the lower word partial product and the lower carry word partial product, and a eighth step for transmitting the carry outputted in the sixth step to the seventh step in accordance with the high level word control signal.
The features and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.